Application specific integrated circuits / Michael John Sebastian Smith.

Title
Application specific integrated circuits / Michael John Sebastian Smith.
Author
Smith, Michael John Sebastian.
Publication
Reading, Mass. : Addison-Wesley, 1997.

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TextUse in libraryRequestTK7874.6 .S63 1997Offsite

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Description
xiv, 1026 p. : ill.; 24 cm.
Bibliography (note)
  • Includes bibliographical references and index.
Processing Action (note)
  • committed to retain
Contents
  • 1. Introduction To Asics -- 1.1. Types of ASIC -- Full-Custom ASICs -- Standard-Cell? Based ASICs -- Gate-Array? Based ASICs -- Channeled Gate-Array -- Channelless Gate-Array -- Structured Gate-Array -- Programmable Logic Devices -- Field-Programmable Gate Arrays -- 1.2. Design Flow -- 1.3. Case Study -- 1.4. Economics of ASICs -- Comparison Between ASIC Technologies -- Product Cost -- ASIC Fixed Costs -- ASIC Variable Costs -- 1.5. ASIC Cell Libraries -- 1.6. Summary -- 1.7. Problems -- 1.8. Bibliography -- 1.9. References2 CMOS LOGIC -- 2.1. CMOS Transistors -- P-Channel Transistors -- Velocity Saturation -- SPICE Models -- Logic Levels -- 2.2. The CMOS Process -- Sheet Resistance -- 2.3. CMOS Design Rules -- 2.4. Combinational Logic Cells -- Pushing Bubbles -- Drive Strength -- Transmission Gates -- Exclusive-OR Cell -- 2.5. Sequential Logic Cells -- Latch -- Flip-Flop -- Clocked Inverter -- 2.6. Datapath Logic Cells -- Datapath Elements -- Adders -- A Simple Example -- Multipliers -- Other Arithmetic Systems -- Other Datapath Operators -- 2.7. I /O Cells -- 2.8. Cell Compilers -- 2.9. Summary -- 2.10. Problems -- 2.11. Bibliography -- 2.12. References3 ASIC LIBRARY DESIGN -- 3.1. Transistors as Resistors -- 3.2. Transistor Parasitic Capacitance -- Junction Capacitance -- Overlap Capacitance -- Gate Capacitance -- Input Slew Rate -- 3.3. Logical Effort -- Predicting Delay -- Logical Area and Logical Efficiency -- Logical Paths -- Multistage Cells -- Optimum Delay -- Optimum Number of Stages -- 3.4. Library-Cell Design -- 3.5. Library Architecture -- 3.6. Gate-Array Design -- 3.7. Standard-Cell Design -- 3.8. Datapath-Cell Design -- 3.9. Summary -- 3.10. Bibliography -- 3.11. Problems -- 3.12. References4 PROGRAMMABLE ASICs -- 4.1. The Antifuse -- Metal?Metal Antifuse -- 4.2. Static RAM -- 4.3. EPROM and EEPROM Technology -- 4.4. Practical Issues -- FPGAs in Use -- 4.5. Specifications -- 4.6. PREP Benchmarks -- 4.7. FPGA Economics -- FPGA Pricing -- Pricing Examples -- 4.8. Summary -- 4.9. Problems -- 4.10. Bibliography -- 4.11. References5 PROGRAMMABLE ASIC LOGIC CELLS -- 5.1. Actel -- ACT 1 Logic Module -- Shannon,s Expansion Theorem -- Multiplexer Logic as Function Generators -- ACT 2 and ACT 3 Logic Modules -- Timing Model and Critical Path -- Speed Grading -- Worst-Case Timing -- Actel Logic Module Analysis -- 5.2. Xilinx LCA -- Xc3000 Clb -- XC4000 Logic Block -- XC5200 Logic Block -- Xilinx CLB Analysis -- 5.3. Altera FLEX -- 5.4. Altera MAX -- Logic Expanders -- Timing Model -- Power Dissipation in Complex PLDs -- 5.5. Summary -- 5.6. Problems -- 5.7. Bibliography -- 5.8. References6 PROGRAMMABLE ASIC I /O CELLS -- 6.1. DC Output -- Totem-Pole Output -- Clamp Diodes -- 6.2. AC Output -- Supply Bounce -- Transmission Lines -- 6.3. DC Input -- Noise Margins -- Mixed-Voltage Systems -- 6.4. AC Input -- Metastability -- 6.5. Clock Input -- Registered Inputs -- 6.6. Power Input -- Power Dissipation -- Power-On Reset -- 6.7. Xilinx I /O Block -- Boundary Scan -- 6.8. Other I /O Cells -- 6.9. Summary -- 6.10. Problems -- 6.11. Bibliography -- 6.12. References7 PROGRAMMABLE ASIC INTERCONNECT -- 7.1. Actel ACT -- Routing Resources -- Elmore's Constant -- RC Delay in Antifuse Connections -- Antifuse Parasitic Capacitance -- ACT 2 and ACT 3 Interconnect -- 7.2. Xilinx LCA -- 7.3. Xilinx EPLD -- 7.4. Altera MAX 5k and 7k -- 7.5. Altera MAX 9k -- 7.6. Altera FLEX -- 7.7. Summary -- 7.8. Problems -- 7.9. Bibliography -- 7.10. References8 PROGRAMMABLE ASIC DESIGN SOFTWARE -- 8.1. Design Systems -- Xilinx -- Actel -- Altera -- 8.2. Logic Synthesis -- FPGA Synthesis -- 8.3. The Halfgate ASIC -- Xilinx -- Actel -- Altera -- Comparison -- 8.4. Summary -- 8.5. Problems -- 8.6. Bibliography -- FPGA Vendors -- Third-party Software -- 8.7. References -- 9. Low-Level Design Entry -- 9.1. Schematic Entry -- Hierarchical Design -- The Cell Library -- Names -- Schematic Icons and Symbols -- Nets -- Schematic Entry for ASICs and PCBs -- Connections -- Vectored Instances and Buses -- Edit-in-Place -- Attributes -- Netlist Screener -- Schematic-Entry Tools -- Back-Annotation -- 9.2. Low-level Design Languages -- Abel -- Cupl -- Palasm -- 9.3. PLA Tools -- 9.4. Edif -- EDIF Syntax -- An EDIF Netlist Example -- An EDIF Schematic Icon -- An EDIF Example -- 9.5. CFI Design Representation -- CFI Connectivity Model -- 9.6. Summary -- 9.7. Bibliography -- 9.8. Problems -- 9.9. References10 VHDL -- 10.1. A Counter -- 10.2. A 4-bit Multiplier -- An 8-bit Adder -- A Register-Accumulator -- Zero-Detector -- A Shift-Register -- A State Machine -- A Multiplier -- Packages and Test Bench -- 10.3. Syntax and Semantics of VHDL -- 10.4. Identifiers and Literals -- 10.5. Entity and Architecture -- 10.6. Packages and Libraries -- Standard Package -- Std_logic_1164 Package -- Textio Package -- Other Packages -- Creating Packages -- 10.7. Interface Declaration -- Port Declaration -- Generics -- 10.8. Type Declaration -- 10.9. Other Declarations -- Object Declarations -- Subprogram Declarations -- Alias and Attribute Declarations -- Predefined Attributes -- 10.10. Sequential Statements -- Wait Statement -- Assertion and Report Statements -- Assignment Statements -- Procedure Call -- If Statement -- Case Statement -- Other Sequential Control Statements -- 10.11. Operators -- 10.12. Arithmetic -- IEEE Synthesis Packages -- 10.13. Concurrent Statements -- Block Statement -- Process Statement -- Concurrent Procedure Call -- Concurrent Signal Assignment -- Concurrent Assertion Statement -- Component Instantiation -- Generate Statement -- 10.14. Execution -- 10.15. Configurations and Specifications -- 10.16. An Engine Controller -- 10.17. Summary -- 10.18. Bibliography -- 10.19. Problems -- 10.20. References
  • 11. VERILOG HDL -- 11.1. A Counter -- 11.2. Basics of the Verilog Language -- Verilog Logic Values -- Verilog Data Types -- Other Wire Types -- Numbers -- Negative Numbers -- Strings -- 11.3. Operators -- Arithmetic -- 11.4. Hierarchy -- 11.5. Procedures and Assignments -- Continuous Assignment Statement -- Sequential Block -- Procedural Assignments -- 11.6. Timing Controls and Delay -- Timing Control -- Data Slip -- Wait Statement -- Blocking and Non-blocking Assignments -- Procedural Continuous Assignment -- 11.7. Tasks and Functions -- 11.8. Control Statements -- Case and If Statement -- Loop Statement -- Disable -- Fork and Join -- 11.9. Logic Gate Modeling -- Built-in Logic Models -- User-defined Primitives -- 11.10. Modeling Delay -- Net and Gate Delay -- Pin-to-pin Delay -- 11.11. Altering Parameters -- 11.12. A Viterbi Decoder -- Viterbi Encoder -- The Received Signal -- Testing the System -- Verilog Decoder Model -- 11.13. Other Verilog Features -- Display Tasks -- File I /O Tasks -- Timescale, Simulation, and Timing Check Tasks -- PLA Tasks -- Stochastic Analysis Tasks -- Simulation Time Functions -- Conversion Functions -- Probability Distribution Functions -- Programming Language Interface -- 11.14. Summary -- 11.15. Bibliography -- 11.16. Problems -- The Viterbi Decoder -- 11.17. References -- 12. Logic Synthesis -- 12.1. A Logic-Synthesis Example -- 12.2. A Comparator /MUX -- An Actel Version of the Comparator /MUX -- 12.3. Inside a Logic Synthesizer -- 12.4. Synthesis of the Viterbi Decoder -- Asic I /O -- Flip-Flops -- The Top-Level Model -- 12.5. Verilog and Logic Synthesis -- Verilog Modeling -- Delays in Verilog -- Blocking and Nonblocking Assignments -- Combinational Logic in Verilog -- Multiplexers In Verilog -- The Verilog Case Statement -- Decoders In Verilog -- Priority Encoder in Verilog -- Arithmetic in Verilog -- Sequential Logic in Verilog -- Component Instantiation in Verilog -- Datapath Synthesis in Verilog -- 12.6. VHDL and Logic Synthesis -- Initialization and Reset -- Combinational Logic Synthesis in VHDL -- Multiplexers in VHDL -- Decoders in VHDL -- Adders in VHDL -- Sequential Logic in VHDL -- Instantiation in VHDL -- Shift Registers and Clocking in VHDL -- Adders and Arithmetic Functions -- Adder-subtracter and Don,t Cares -- 12.7. Finite-State Machine Synthesis -- FSM Synthesis in Verilog -- FSM Synthesis in VHDL -- 12.8. Memory Synthesis -- Memory Synthesis in Verilog -- Memory Synthesis in VHDL -- 12.9. The Multiplier -- Messages During Synthesis -- 12.10. The Engine Controller -- 12.11. Performance-Driven Synthesis -- 12.12. Optimization of the Viterbi Decoder -- 12.13. Summary -- 12.14. Problems -- 12.15. Bibliography -- 12.16. References13 SIMULATION -- 13.1. The Different Types of Simulation -- 13.2. The Comparator /MUX Example -- Structural Simulation -- Static Timing Analysis -- Gate-Level Simulation -- Net Capacitance -- 13.3. Logic Systems -- Signal Resolution -- Logic Strength -- 13.4. How Logic Simulation Works -- VHDL Simulation Cycle -- Delay -- 13.5. Cell Models -- Primitive Models -- Synopsys Models -- Verilog Models -- VHDL Models -- VITAL Models -- SDF in Simulation -- 13.6. Delay Models -- Using a Library Data Book -- Input-Slope Delay Model -- Limitations of Logic Simulation -- 13.7. Static Timing Analysis -- Hold Time -- Entry Delay -- Exit Delay -- External Setup Time -- 13.8. Formal Verification -- An Example -- Understanding Formal Verification -- Adding an Assertion -- Completing a Proof -- 13.9. Switch-Level Simulation -- 13.10. Transistor-Level Simulation -- A PSpice Example -- SPICE Models -- 13.11. Summary -- 13.12. Problems -- 13.13. Bibliography -- 13.14. References14 TEST -- 14.1. The Importance of Test -- 14.2. Boundary-Scan Test -- BST Cells -- BST Registers -- Instruction Decoder -- TAP Controller -- Boundary-Scan Controller -- A Simple Boundary-Scan Example -- Bsdl -- 14.3. Faults -- Reliability -- Fault Models -- Physical Faults -- Stuck-at Fault Model -- Logical Faults -- IDDQ Test -- Fault Collapsing -- Fault Collapsing Example -- 14.4. Fault Simulation -- Serial Fault Simulation -- Parallel Fault Simulation -- Concurrent Fault Simulation -- Nondeterministic Fault Simulation -- Fault-Simulation Results -- Fault-Simulator Logic Systems -- Hardware Acceleration -- A Fault Simulation Example -- Fault Simulation in an ASIC Design Flow -- 14.5. Automatic Test-Pattern Generation -- The D-Calculus -- A Basic ATPG Algorithm -- The PODEM Algorithm -- Controllability and Observability -- 14.6. Scan Test -- 14.7. Built-in Self-test -- Lfsr -- Signature Analysis -- A Simple BIST Example -- Aliasing -- LFSR Theory -- LFSR Example -- Misr -- 14.8. A Simple Test Example -- Test Logic Insertion -- How the Test Software Works -- ATVG and Fault Simulation -- Test Vectors -- Production Tester Vector Formats -- Test Flow -- 14.9. The Viterbi Decoder Example -- 14.10. Summary -- 14.11. Problems -- 14.12. Bibliography -- 14.13. References15 ASIC CONSTRUCTION -- 15.1. Physical Design -- 15.2. CAD Tools -- Methods and Algorithms -- 15.3. System Partitioning -- 15.4. Estimating ASIC Size -- 15.5. Power Dissipation -- Switching Current -- Short-Circuit Current -- Subthreshold and Leakage Current -- 15.6. FPGA Partitioning -- ATM Simulator -- Automatic Partitioning with FPGAs -- 15.7. Partitioning Methods -- Measuring Connectivity -- A Simple Partitioning Example -- Constructive Partitioning -- Iterative Partitioning Improvement -- The Kernighan?Lin Algorithm -- The Ratio-Cut Algorithm -- The Look-ahead Algorithm -- Simulated Annealing -- Other Partitioning Objectives -- 15.8. Summary -- 15.9. Problems -- 15.10. Bibliography -- 15.11. References16 FLOORPLANNING AND PLACEMENT -- 16.1. Floorplanning -- Floorplanning Goals and Objectives -- Measurement of Delay in Floorplanning -- Floorplanning Tools -- Channel Definition -- I /O and Power Planning -- Clock Planning -- 16.2. Placement -- Placement Terms and Definitions -- Placement Goals And Objectives -- Measurement of Placement Goals and Objectives -- Placement Algorithms -- Eigenvalue Placement Example -- Iterative Placement Improvement -- Placement Using Simulated Annealing -- Timing-Driven Placement Methods -- A Simple Placement Example -- 16.3. Physical Design Flow -- 16.4. Information Formats -- SDF for Floorplanning and Placement -- Pdef -- Lef and Def -- 16.5. Summary -- 16.6. Problems -- 16.7. Bibliography -- 16.8. References17 ROUTING -- 17.1. Global Routing -- Goals and Objectives -- Measurement of Interconnect Delay -- Global Routing Methods -- Global Routing Between Blocks -- Global Routing Inside Flexible Blocks -- Timing-Driven Methods -- Back-annotation -- 17.2. Detailed Routing -- Goals and Objectives -- Measurement of Channel Density -- Algorithms -- Left-Edge Algorithm -- Constraints and Routing Graphs -- Area-Routing Algorithms -- Multilevel Routing -- Timing-Driven Detailed Routing -- Final Routing Steps -- 17.3. Special Routing -- Clock Routing -- Power Routing -- 17.4. Circuit Extraction and DRC -- Spf, Rspf and Dspf -- Design Checks -- Mask Preparation -- 17.5. Summary -- 17.6. Problems -- 17.7. Bibliography -- 17.8. References.
ISBN
0201500221
LCCN
^^^93032538^
Owning Institutions
Harvard Library