Research Catalog
Digital systems design with VHDL and synthesis : an integrated approach / K.C. Chang.
- Title
- Digital systems design with VHDL and synthesis : an integrated approach / K.C. Chang.
- Author
- Chang, K. C. (Kou-Chuan), 1957-
- Publication
- Los Alamitos, Calif. : IEEE Computer Society, 1999.
Items in the Library & Offsite
About 1 Item. Still Loading More items...
Format | Access | Status | Call Number | Location |
---|---|---|---|---|
Text | Use in library | Request | TK7888.4 .C435 1999 | Offsite |
Details
- Description
- xv, 499 p. : ill.; 26 cm.
- Subject
- Bibliography (note)
- Includes bibliographical references and index.
- Processing Action (note)
- committed to retain
- Contents
- Integrated Design Process and Methodology -- VHDL and Digital Circuit Primitives -- Flip Flop -- Latch -- Three-State Buffer -- Combinational Gates -- VHDL Synthesis Rules -- Pads -- VHDL Simulation and Synthesis Environment and Design Process -- Synopsys VHDL Simulation Environment Overview -- Mentor Quick VHDL Simulation Environment -- Synthesis Environment -- Synthesis Technology Library -- VHDL Design Process for a Block -- Basic Combinational Circuits -- Selector -- Encoder -- Code Converter -- Equality Checker -- Comparator with Single Output -- Comparator with Multiple Outputs -- Basic Binary Arithmetic Circuits -- Half Adder and Full Adder -- Carry Ripple Adder -- Carry Look Ahead Adder -- Countone Circuit -- Leading Zero Circuit -- Barrel Shifter -- Basic Sequential Circuits -- Signal Manipulator -- Counter -- Shift Register -- Parallel to Serial Converter -- Serial to Parallel Converter -- Registers -- General Framework for Designing Registers -- Interrupt Registers -- DMA and Control Registers -- Configuration Registers -- Reading Registers -- Register Block Partitioning and Synthesis -- Testing Registers -- Microprocessor Registers -- Clock and Reset Circuits -- Clock Buffer and Clock Tree -- Clock Tree Generation -- Reset Circuitry -- Clock Skew and Fixes -- Synchronization between Clock Domains -- Clock Divider -- Gated Clock -- Dual-Port RAM, FIFO, and Dram Modeling -- Dual-Port RAM -- Synchronous FIFO -- Asynchronous FIFO -- Dynamic Random Access Memory (DRAM).
- ISBN
- 0769500234
- LCCN
- ^^^99024750^
- Owning Institutions
- Harvard Library